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in Valencia is seeking a Senior Design Engineer to develop logic IPs (standard cells and IOs) for analog, digital and mixed-signal SOC designs across technology nodes.
You will design, simulate, and layout logic cells and contribute to library development.
Idóneo candidates have 3+ years in EE, a Master’s in EE, strong circuit design, library verification, and scripting skills. xghoner
You will debug issues and automate validation in a collaborative, global team.
📌 Senior Foundation IP Design Engineer (Valencia)
🏢 Analog Devices
📍 Valencia
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