Capgemini Engineering Madrid is seeking a Senior RTL Engineer to lead feasibility studies, define system architecture and interfaces, and drive design from architecture to tape-out.
Si le interesa solicitar este empleo, por favor, asegúrese de cumplir los siguientes requisitos que se enumeran a continuación.
You will perform RTL coding in Verilog/SystemVerilog (or VHDL), develop microarchitecture, and collaborate with Synthesis, STA, PD, and DFT teams to meet timing, power and area goals. xqbhyrx
You'll benefit from a collaborative culture, versátil growth opportunities, and a comprehensive benefits package in a global
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Hay opciones de teletrabajo/trabajo desde casa disponibles para este puesto.