GMV Spain is expanding its GNSS‑User Segment Navigation team to migrate an architecture from Xilinx MPSoC/FPGA to an ASIC solution.
¿Tiene su CV preparado? Si es así y confía en que este es el puesto adecuado para usted, asegúrese de enviar su solicitud lo antes posible.
The role emphasizes RTL development, IP integration, and extensive ASIC flow activities in a cutting-edge hardware environment.
We value candidates with hands-on experience in digital hardware programming, SystemVerilog-based verification, and familiarity with industry tools (Synopsys, Cadence, Vivado). xcskxlj
Hybrid working model and relocation support offered.