We are seeking a Senior Formal Verification (FV) Engineer to own the formal verification environment for our next‑generation, high‑performance Out‑of‑Order (OoO) RISC‑V Vector Unit (VU). You will be the dedicated formal expert for the VU team, responsible for designing scalable formal testbenches, writing mathematical properties, and ensuring the absolute algorithmic and architectural integrity of our vector pipeline. Block‑Level Execution & Convergence Engineering (90%) Formal‑Friendly Design: Partner with VU microarchitects during early‑stage RTL development to drive formal‑friendly coding styles and structural design patterns.

S. in Computer Engineering, Electrical Engineering, or Computer Science with practical industry execution;

Experience: 5+ years of production‑grade hardware verification experience (or Ph.Familiarity with control‑path formal techniques (liveness, safety properties) is highly welcome.

Formal Tools: Proficient command of commercial EDA formal tools (e.g., Scripting proficiency (Python, Tcl, or Bash) for testbench automation. Clear communication across DV, design, and software teams; 4 days per week in the Barcelona office (city center), 1 WFH. ~

📌 Senior Hardware Verification Engineer (Barcelona)
🏢 Semidynamics
📍 Barcelona