ppPrincipal Physical Design Engineer (Full Chip Expert) /p /brpbLocation: /b Integral / Hybridbr/bDepartment: /b Engineeringbr/bReports to: /b Physical Design Function Lead /p /brpJoin Aion Silicon and Shape the Future of Semiconductor Innovation /p /brpAt Aion Silicon, we're seeking an experienced bPrincipal Physical Design Engineer /b to lead the physical implementation of complex, cutting‑edge SoCs and ASICs. This is a senior technical leadership role for a recognised Full‑Chip Physical Design expert who thrives on solving complex challenges, mentoring engineering teams, and driving successful tape‑outs on advanced technology nodes. /p /brpYou will take ownership of the complete physical design flow, from RTL/netlist handoff through to final sign‑off and GDSII generation, working closely with cross‑functional teams across the globe. /p /brh3What You'll Be Doing /h3 /brul /br liLead full-chip physical implementation for complex SoC and ASIC designs. /li /br liDefine and drive chip‑level physical design strategies, methodologies and best practices. /li /br liCoordinate closely with RTL, STA, DFT, Packaging, Foundry and EDA partners to achieve successful design closure. /li /br liMentor and coach Physical Design engineers, supporting capability development across the team. /li /br liReview and approve block‑level physical design deliverables before integration. /li /br liLead technical reviews, debug sessions and closure activities. /li /br liSupport recruitment activities and contribute to building a world‑class Physical Design team. /li /br liRepresent Aion Silicon at universities, conferences and industry events, sharing technical expertise and promoting innovation. /li /br liEnsure the team remains at the forefront of industry methodologies, tools and advanced‑node technologies.



/li /br /ul /brh3What We're Looking For /h3 /brul /br li10+ years of Physical Design experience with a proven track record of full-chip delivery. /li /br liStrong expertise in advanced technology nodes, including 7nm, 5nm and below. /li /br liExperience delivering multiple complex SoC or ASIC tape‑outs. /li /br liDemonstrated leadership experience mentoring and developing engineers. /li /br liStrong customer engagement and stakeholder management skills. /li /br liExcellent communication skills with the ability to influence technical direction across multiple teams. /li /br /ul /brh3Technical Expertise /h3 /brh3Full‑Chip Floorplanning Integration /h3 /brul /br liChip‑level floorplanning and macro placement /li /br liIO ring integration /li /br liHierarchical and flat implementation flows /li /br liPin placement, channel planning and congestion management /li /br /ul /brh3Power Planning Package Integration /h3 /brul /br liPower grid design and optimisation /li /br liMulti‑voltage domains and power gating /li /br liIR drop and electromigration analysis /li /br liBump planning and package co‑design /li /br /ul /brh3Clock Tree Synthesis /h3 /brul /br liMulti‑domain and multi‑level CTS /li /br liClock mesh, H‑tree and fishbone architectures /li /br liSkew, latency and jitter optimisation /li /br liLow‑power clocking techniques /li /br /ul /brh3Placement, Routing Timing Closure /h3 /brul /br liFull‑chip placement and routing /li /br liSignal integrity,



crosstalk and antenna resolution /li /br liMCMM timing analysis /li /br liSTA sign‑off and timing ECO implementation /li /br liHierarchical timing budgeting and closure /li /br /ul /brh3Physical Verification Tape‑Out /h3 /brul /br liDRC, LVS and ERC sign‑off /li /br liRC extraction and correlation /li /br liReliability and noise analysis /li /br liGDSII/OASIS generation and foundry handoff /li /br /ul /brh3EDA Tool Expertise /h3 /brpStrong working knowledge of one or more industry‑leading tool flows, including: /p /brul /br liSynopsys (ICC2, Fusion Compiler, PrimeTime, StarRC, ICV) /li /br liCadence (Innovus, Tempus, Voltus, Genus) /li /br liMentor Calibre /li /br /ul /brh3Desirable Experience /h3 /brul /br liDFT integration and ECO flows /li /br li2.5D/3D‑IC and chiplet‑based architectures /li /br liAdvanced packaging technologies /li /br liMaster's or PhD in a relevant engineering discipline /li /br /ul /brh3Personal Attributes /h3 /brul /br liLeads through collaboration, trust and transparency. /li /br liThrives in a fast‑paced environment and enjoys solving complex technical challenges. /li /br liDemonstrates strong ownership and accountability. /li /br liHas a passion for mentoring and developing others. /li /br liIs adaptable, resilient and able to navigate changing priorities. /li /br liEmbodies Aion Silicon's values and contributes positively to our culture. /li /br /ul /brh3Why Join Aion Silicon? /h3 /brpAt Aion Silicon, you'll work alongside exceptional engineers on some of the industry's most challenging semiconductor projects. You'll have the opportunity to influence technical strategy, mentor future talent, and help shape the next generation of silicon solutions. /p /brpIf you're a recognised Full‑Chip Physical Design expert ready to make a significant impact, we'd love to hear from you. /p /brpbApply today and help us design the future. /b /p /p #J-18808-Ljbffr

📌 Principal Physical Design Engineer (Full Chip Expert) (Barcelona)
🏢 Aion Silicon
📍 Barcelona