pThe TMRW Foundation SILICON is seeking a skilled Digital IC Designer to develop, simulate, and verify complex digital ICs using a Cadence-centric flow. You will implement RTL in VHDL/Verilog, perform functional verification, and drive synthesis and physical implementation tasks across floorplanning, placement, and routing. /ppResponsibilities include timing closure with Tempus, DRC/LVS verification, and close collaboration with architects, analog designers, and layout engineers. /p #J-18808-Ljbffr
📌 Senior Digital IC Designer - RTL, Verilog, Cadence (Madrid)
🏢 TMRW
📍 Madrid