Job Description Our client is expanding their hardware
engineering team and is looking for experienced engineers with a
strong background in memory subsystem design. This role focuses on
developing and integrating high performance memory solutions within
advanced processor environments. You will work closely with
architecture, RTL and verification teams to design efficient and
scalable memory subsystems, contributing to complex chip
development projects. Location : Barcelona, Spain - Hybrid
Responsibilities: As a Senior / Lead DDR Engineer , your broad
responsibilities will include but are not limited to: Senior DDR
Engineer Design and develop memory subsystems, including DDR or HBM
based solutions Implement and integrate memory controllers within
SoC or ASIC environments Work with AXI based interfaces and system
level interconnects Develop RTL using Verilog or VHDL based on
architecture specifications Apply timing constraints and support
timing closure activities Perform block level testing and
validation Collaborate with cross functional teams to ensure design
quality and performance Additional Responsibilities for Lead DDR
Engineer Define memory subsystem architecture and technical
direction Own delivery and quality of memory related blocks across
project milestones Drive design decisions and trade offs at system
level Coordinate work across RTL, verification and integration
teams Mentor and support engineers within the team Act as
escalation point for complex technical challenges Contribute to
long term roadmap planning for memory subsystems Requirements:
Senior DDR Engineer 8+ years of industrial experience in relevant
roles Strong experience with DDR or HBM memory systems Proven
background in memory controller design or integration Experience
with AXI or AMBA protocols Solid RTL design skills using Verilog or
VHDL Experience with timing constraints and timing analysis
Understanding of block level testing methodologies Additional
Requirements for Lead DDR Engineer Proven experience leading
technical projects or small teams Strong ownership of complex
memory subsystem design or integration Ability to define
architecture and drive technical decisions Experience coordinating
cross functional engineering efforts Strong communication and
mentoring skills Nice to have: Master or PhD in a relevant field
Scripting experience with Python, Perl, Bash or TCL Experience with
version control systems (git, svn) Understanding of coherency
concepts and protocols Experience with memory map definition What’s
in it for you? Our client offers an exciting, challenging role in a
collaborative, dynamic environment. The right person will find many
career growth opportunities in their company, whether you want to
advance your technical skills or aspire to leadership in the
future. Benefits: Versátil working hours (office open between 7 AM
and 9 PM, employees manage their own schedule) Hybrid working model
One week per year work from anywhere 25 days annual leave plus
December 24 and 31 €150 per month food allowance (≈ €1800 per year
additional compensation) Private medical insurance One time
relocation bonus paid with the first salary Support with housing
search through an agency Visa support if required Relocation
support for family Virtual shares Language classes (Spanish,
English, Catalan) Tax incentive