30 jul
|
Capgemini
|
Madrid
Capgemini Engineering is seeking a Senior RTL Engineer to own feasibility studies, define system architecture, and develop microarchitecture and logic for complex designs. You will code RTL, perform lint and CDC checks, and generate timing constraints in collaboration with synthesis and STA teams. You’ll work closely with PD, DFT, and design leads to meet performance, power, and area targets while contributing to tool flows and design methodologies.
📌 Senior RTL Engineer — Flexible Hours, SoC & VLSI (Madrid)
🏢 Capgemini
📍 Madrid