13 nov
|
Capgemini Engineering
|
Madrid
13 nov
Capgemini Engineering
Madrid
Grupo Oesía is seeking a DFT Engineer to design, implement and optimize test strategies for ASICs/SoCs. You will work in a multidisciplinary team to develop robust test architectures and ensure high coverage across complex silicon.
Your role spans design collaboration, ATPG/MBIST/LBIST validation, and integration with verification and physical implementation teams, with opportunities to contribute to cutting-edge projects across strategic sectors.
📌 Dft Engineer For Asics (Madrid)
🏢 Capgemini Engineering
📍 Madrid