Hireroo Ltd is seeking a Lead Design Verification Engineer in Barcelona, Spain, with hybrid work style (4 days in office, 1 day from home). You will own verification strategy and UVM environments for DDR/LPDDR memory interfaces across ASIC/SoC designs. Lead a team, mentor engineers, and collaborate with RTL, architecture and firmware teams to ensure functional correctness and protocol compliance.
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📌 Lead DDR/LPDDR Verification Architect (UVM) (Madrid)
🏢 Hireroo
📍 Madrid
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