Specialization: Semiconductor Design and Functional Verification Job Description Our partner is looking for a

Lead Design Verification Engineer

to lead functional verification of DDR/LPDDR memory interfaces within complex ASIC and SoC designs.

You will take ownership of

verification strategy, UVM environments and coverage closure , ensuring functional correctness and protocol compliance.

This is a technical leadership role involving direct verification work, mentoring engineers and collaborating with RTL, architecture and firmware teams.

Location:

Barcelona, Spain

Working model:

Hybrid, 4 days in the office, 1 day from home

Employment:

Full time

Responsibilities

Lead functional verification of

DDR/LPDDR memory interfaces

at IP and subsystem levels.

Develop and maintain

SystemVerilog/UVM testbenches .

Define verification strategies, coverage plans and signoff criteria.

Verify DDR/LPDDR and AMBA protocol compliance.

Debug RTL, testbench and specification mismatches.

Manage regressions, investigate failures and drive bug closure.

Optimize simulation performance and automate verification workflows.

Guide verification engineers and collaborate across engineering teams.

Maintain verification documentation and methodologies.

Mandatory Requirements

10+ years in ASIC/SoC functional verification .

Recent





DDR/LPDDR or comparable high speed protocol verification

experience.

Strong

AMBA protocol knowledge , including AXI, AHB, CHI or CXS.

Advanced

SystemVerilog, UVM and coverage closure

experience.

Experience with

VCS, Xcelium or Questa .

Strong RTL debugging and SoC architecture knowledge.

Proven

technical leadership and team coordination .

Relevant engineering degree.

Important:

Direct ASIC/SoC functional verification experience, including UVM development, protocol expertise and verification signoff ownership, is essential. RTL design or physical verification alone is insufficient.

Optional / Desired

Python, Perl or TCL scripting.

Git, Perforce, LSF or Grid Engine.

AI tools for verification automation and regression analysis.

Experience with PCIe, UCIe or SerDes.

Strong documentation and communication skills.

What's in it for you?

Versátil working hours

Hybrid model, 4 days office, 1 day from home

1 week per year working from anywhere

25 days annual leave plus December 24 and 31

Monthly food allowance

Private medical insurance

Relocation bonus

Housing search support

Visa support, subject to approval

Family relocation support, subject to eligibility

Virtual shares, subject to plan terms

Language classes

Tax incentive

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