Specialization: Semiconductor Design and Functional VerificationJob DescriptionOur partner is looking for aLead Design Verification Engineerto lead functional verification of DDR/LPDDR memory interfaces within complex ASIC and SoC designs.You will take ownership ofverification strategy, UVM environments and coverage closure, ensuring functional correctness and protocol compliance.This is a technical leadership role involving direct verification work, mentoring engineers and collaborating with RTL, architecture and firmware teams.Location:Barcelona, SpainWorking model:Hybrid, 4 days in the office, 1 day from homeEmployment:Full timeResponsibilitiesLead functional verification ofDDR/LPDDR memory interfacesat IP and subsystem levels.Develop and maintainSystemVerilog/UVM testbenches .Define verification strategies, coverage plans and signoff criteria.Verify DDR/LPDDR and AMBA protocol compliance.Debug RTL, testbench and specification mismatches.Manage regressions,



investigate failures and drive bug closure.Optimize simulation performance and automate verification workflows.Guide verification engineers and collaborate across engineering teams.Maintain verification documentation and methodologies.Mandatory Requirements10+ years in ASIC/SoC functional verification .RecentDDR/LPDDR or comparable high speed protocol verificationexperience.StrongAMBA protocol knowledge, including AXI, AHB, CHI or CXS.AdvancedSystemVerilog, UVM and coverage closureexperience.Experience withVCS, Xcelium or Questa .Strong RTL debugging and SoC architecture knowledge.Proventechnical leadership and team coordination .Relevant engineering degree.Important:Direct ASIC/SoC functional verification experience, including UVM development, protocol expertise and verification signoff ownership, is essential. RTL design or physical verification alone is insufficient.Optional / DesiredPython, Perl or TCL scripting.Git, Perforce, LSF or Grid Engine.AI tools for verification automation and regression analysis.Experience with PCIe, UCIe or SerDes.Strong documentation and communication skills.What's in it for you?Versátil working hoursHybrid model, 4 days office, 1 day from home1 week per year working from anywhere25 days annual leave plus December 24 and 31Monthly food allowancePrivate medical insuranceRelocation bonusHousing search supportVisa support, subject to approvalFamily relocation support, subject to eligibilityVirtual shares, subject to plan termsLanguage classesTax incentive#J-18808-Ljbffr

📌 Lead Digital Verification Eng. - Ddr/Lpddr Protocols (Madrid)
🏢 Hireroo
📍 Madrid