Specialization: Semiconductor Design and Functional Verification

Job Description

Our partner is looking for a Staff Design Verification Engineer to develop and improve functional verification environments for complex ASIC and SoC designs, focusing on PCIe, UCIe, SerDes and AMBA protocols .

You will take technical ownership of SystemVerilog/UVM testbenches, protocol verification, debugging and coverage closure , ensuring functional correctness and efficient verification processes.

This is a senior technical role requiring independent problem solving, protocol expertise and collaboration with RTL and architecture teams.

Location: Barcelona, Spain

Working model: Hybrid, 4 days in the office, 1 day from home

Employment: Full time

Responsibilities

- Develop and debug ASIC/SoC verification environments at IP and subsystem levels.

- Build and maintain SystemVerilog/UVM testbenches .

- Verify PCIe, UCIe, SerDes and AMBA protocols .

- Investigate RTL, verification model and specification mismatches.

- Drive functional coverage, regressions and bug closure.

- Improve simulation performance and automate verification workflows.

- Resolve complex verification issues with engineering teams.

- Maintain verification documentation and methodologies.

Mandatory Requirements

- 7+ years in ASIC/SoC functional verification .

- Recent PCIe,



UCIe or SerDes verification experience.

- Strong AMBA knowledge , including AXI, CHI, CXS or AHB.

- Advanced SystemVerilog, UVM and coverage closure skills.

- Experience with VCS, Xcelium or Questa .

- Strong RTL debugging and SoC architecture knowledge.

- Independent technical ownership and complex problem solving.

- Relevant engineering degree.

Important: Direct ASIC/SoC functional verification experience, including UVM development and protocol debugging, is essential. RTL design, FPGA development or physical verification alone is insufficient.

Optional / Desired

- Python, Perl or TCL scripting.

- Git, Perforce, LSF or Grid Engine.

- AI tools for verification and regression analysis.

- Simulation performance optimization.

- Strong documentation and communication skills.

What's in it for you?

- Versátil working hours

- Hybrid model, 4 days office, 1 day from home

- 1 week per year working from anywhere

- 25 days annual leave plus December 24 and 31

- Monthly food allowance

- Private medical insurance

- Relocation bonus

- Housing search support

- Visa support, subject to approval

- Family relocation support, subject to eligibility

- Virtual shares, subject to plan terms

- Language classes

- Tax incentive

📌 Staff Design Verification Engineer (España)
🏢 Hireroo
📍 España