Grupo Oesía in Madrid is seeking an experienced ASIC digital design engineer to join a multidisciplinary team. You will design, develop and integrate high-value So C solutions, contributing from RTL coding to verification and collaboration with multiple disciplines.The role emphasizes Verilog/System Verilog, RTL design, UVM verification, and collaboration across design, verification and physical implementation teams, with opportunities to influence architecture and silicon validation in strategic#J-18808-Ljbffr
📌 Senior Rtl/Asic Engineer For High-Value Soc Design (Madrid)
🏢 Oesía Group
📍 Madrid
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