OverviewIn this role you will own the top-level RTL design for high-performance SoCs, guiding cross-functional teams to tape-out-ready designs.
You will shape critical architectures for clock, reset, power, and IO, and drive the design process from specification through integration.
As a hands-on leader, you mentor engineers, set standards, and ensure design excellence across architecture, verification, and physical design.
This position offers impact at scale in a dynamic, cutting-edge semiconductor environment.
Compensaciones / Beneficios4 days per week in Barcelona office + 1 day remote
One week work-from-anywhere
Competitive compensation
Exposure to confidential computing and memory isolation
Growth-oriented, collaborative environment
Direct ownership and clear thinking in a dynamic team
ResponsabilidadesLead integration of CPU clusters, subsystems, and external IP into the SoC top-level RTL
Mentor RTL engineers, plan work, and establish design standards
Define and implement reset architecture with domains, sequencing, and synchronization
Design clock architecture including topology, generation, and distribution
Develop power infrastructure with multiple domains and sequencing
Plan signal distribution, delay propagation, and signal integrity




Define and manage external interfaces including pads, IOs, and low-level cells with ESD protection
Own lint, CDC, and RDC at the SoC top level and drive UPF power intent
Coordinate with architecture, verification, DFT, and physical design teams to progress to tape-out
Requisitos principalesDegree in Electrical Engineering, Electronic Engineering, Computer Engineering, or related field
8+ years in digital/SoC design
Strong hands-on RTL design with SystemVerilog/Verilog
Experience leading SoC top-level RTL integration for large, high-performance designs
Track record of tape-outs for high-performance SoCs
Expertise in SoC clock and reset architectures
Experience with signal distribution and signal integrity
Hands-on experience interfacing with external components including pads and tri-state buffers
Solid understanding of ESD protection concepts
Technical lead experience with mentoring and cross-team coordination
Fluent in English
leadership and mentoring
cross-functional collaboration
clear communication
SystemVerilog/Verilog RTL design
SoC top-level RTL integration
clock and reset architecture

📌 Soc Top Rtl Lead Engineer (Barcelona)
🏢 Intellectual Capital Resources
📍 Barcelona