09 nov
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Beagle
|
Alcobendas
Beagle is seeking an experienced Lead Design Verification Engineer to own the verification of high‑speed interfaces in cutting‑edge AI SoC designs. You will architect SystemVerilog/UVM environments, drive coverage plans, and lead a team toward sign-off.Required are 10+ years in ASIC/SoC verification, deep PCIe/UCIe and AMBA protocol knowledge, and hands‑on ability with SystemVerilog/UVM. Strong leadership and collaboration across RTL, firmware and architecture are essential.#J-18808-Ljbffr
📌 Digital Mixed Signal Verification Engineer (Alcobendas)
🏢 Beagle
📍 Alcobendas