We are looking for experienced Design Verification Engineers to join our semiconductor engineering team and work on challenging IP and So C verification projects.We are particularly interested in engineers with strong experience in Ethernet IP verification, including MAC, PCS and PHY components. Experience with high-speed communication protocols and complex So C verification is highly valued.Key Responsibilities Perform IP, subsystem and system-level verification of complex semiconductor designs.Develop and execute verification plans, test scenarios and testbenches.Verify Ethernet IP, particularly MAC, PCS and PHY blocks.Develop and maintain System Verilog/UVM-based verification environments.Implement tests,



analyze functional coverage and drive coverage closure.Debug simulation failures and collaborate with design teams to resolve issues.Support verification of high-speed interfaces and complex So C architectures.Contribute to regression environments and verification automation. Required Skills & Experience Solid experience in ASIC/So C Design Verification.Strong knowledge of System Verilog and UVM.Hands-on experience with Ethernet IP verification (MAC, PCS and/or PHY) is a major advantage.Experience with block-level and system-level verification.Experience with PCIe verification.Experience with RISC-V or complex So C architectures.Programming skills in C/C++ and/or Python.Experience with Linux and simulation tools.Familiarity with Cadence verification tools. #J-18808-Ljbffr

📌 Senior Design Verification Engineer (Madrid)
🏢 TechTeamz
📍 Madrid