Semidynamics is a Barcelona-based semiconductor company, founded in ****, that designs European processor technology built on the open RISC-V standard. We develop fully customisable 64-bit RISC-V processor IP, including out-of-order and in-order CPU cores and dedicated vector and tensor units, for demanding AI, machine learning and high-performance computing workloads.Our team combines deep architecture expertise with hands-on silicon experience, and we are growing to deliver complete, high-performance SoC solutions to our customers.Role overviewWe are looking for an SoC Top RTL Integration Engineer to integrate multiple subsystems into the top level of our high-performance SoCs. You will connect CPU clusters, IP blocks and peripherals through interconnects and NoCs, and make sure the integrated design is clean, constrained and ready for tape-out.This is a senior, hands-on role for an engineer who has already integrated large SoCs and taken them to silicon.Key responsibilitiesIntegrate multiple subsystems (CPU clusters, memory, accelerators, peripherals and third-party IP) into theSoC top-level RTL .

Connect subsystems throughinterconnects and NoCsusing protocols such asAXI, APBandCHI . Define and integrate the chip'sIOs, including connections topads . Write and maintainSDCtiming constraints for the integrated design, working with physical design teams.Run, debug and closelint, CDC and RDCchecks at SoC top level.Integrate the top-levelclock, resetand power infrastructure,



and contribute toUPFpower intent.Develop Python and C scripts and tests to automate integration flows and support bring-up.Work closely with architecture, verification, DFT and physical design teams to drive the SoC through totape-out .

Required qualificationsDegree in Electrical Engineering, Electronic Engineering, Computer Engineering or a related field.8+ years of experience in digital/SoC design.Strong hands-on RTL design experience (SystemVerilog/Verilog). Proven experience integrating multiple subsystems on large SoCs.Experience connecting subsystems through interconnects and/or NoCs, with solid knowledge of AXI and APB.Proven track record on one or more tape-outs.Hands-on experience with lint, CDC and RDC checks.Experience writing and managing SDC constraints and integrating chip IOs.Working knowledge of Python and C for scripting and automation (user level).

Fluent

English, written and spoken.Nice to haveKnowledge of clock, reset and power architectures.Experience with the CHI coherent interconnect protocol.Experience with UPF-based low-power design flows and pad ring integration.Why SemidynamicsWork at one of Europe's most promising deep-tech semiconductor scale-upsAccelerated development path, with room to grow into confidential computing, memory isolation and software security4 days per week in the Barcelona office (city center), 1 day working from home1 week of work from anywhere in the worldCompetitive packageA collaborative, technical, growth-oriented environment that values direct ownership and clear thinking

📌 (Senior) Integration Engineer (Barcelona)
🏢 Semidynamics
📍 Barcelona