We are seeking a highly motivatedPrincipal STA / Constraints Sign-Off Engineerto lead timing signoff and constraint methodology development for advanced-node SoC and IP designs. The adecuado candidate will have deep expertise in STA, timing constraints, signoff closure, and methodology automation, enabling successful tape-outs with best-in-class quality, performance, power, and area (PPA). This role requires a strong hands-on technical leader who can drive methodology, execution, and signoff while collaborating closely with Architecture, RTL, Verification, DFT and PD team collaboration.

Key Responsibilities Own and drive SoC/IP/blocks timing signoff methodologies across advanced technology nodes. Develop, review, and validate SDC constraints, timing exceptions, and MMMC signoff environments. Lead setup, hold, SI, OCV/AOCV/POCV, and timing closure activities through final signoff.

Drive timing correlation across synthesis, implementation, extraction, and signoff flows. Support ECO closure, low-power timing analysis, and cross-functional signoff activities. Develop automation scripts, methodology documentation, training materials, and best practices.

Collaborate closely with RTL, Physical Design, DFT, CAD, Verification, and IP teams to achieve timing convergence.



Required / Preferred Qualifications BS/MS in Electrical Engineering or related field with 12+ years of experience in STA, timing signoff, and ASIC/SoC implementation. Strong hands-on expertise in PrimeTime, SDC development, MMMC analysis, timing closure, OCV/AOCV/POCV, crosstalk, and ECO methodologies.

Good understanding of ASIC implementation flows, libraries, memories, PDKs, and advanced-node signoff requirements. Strong scripting skills in Tcl, Python, or Perl for flow automation and methodology development. Excellent debugging, analytical, communication, and technical leadership skills.

Experience with advanced-node technologies (7nm/5nm/3nm and below). Knowledge of UPF, low-power design, EMIR, and thermal signoff flows. Familiarity with high-speed protocols such as PCIe, DDR, UCIE,ABB, PLLs and all latest IPs.

Experience driving methodology improvements and mentoring engineering teams.

Tools Required: Synopsys: PrimeTime (PT/PT-SI/PT-PX), ICC2/Fusion Compiler, StarRC, and ICV for STA, signoff, implementation, extraction, and physical verification.

Cadence: Tempus, Innovus, and Voltus for timing analysis, physical implementation, and power integrity signoff.

Scripting: Strong proficiency in Tcl, Python, and Perl for automation, methodology development, and reporting.

📌 Principal Engineer - Sta / Constraints Sign-Off Engineer (Barcelona)
🏢 Aion Silicon
📍 Barcelona