Specialization: Semiconductor Design and SoC IntegrationJob Description

Our partner is looking for aSenior SoC RTL Integration Engineerto bring processor clusters, memory, accelerators and peripherals together into a complete chip design.

You will ownRTL integration at the SoC top level, ensuring that subsystems communicate correctly and that timing constraints, clocks, resets and interfaces are ready for implementation.

The role involves close collaboration with architecture, verification, DFT and physical design teams, taking integrated designs through checks, issue resolution and tapeout.

Location:Barcelona, Spain

Working model:Hybrid, 4 days in the office, 1 day from home

Employment:Full time

Responsibilities

Integrate CPU clusters, memory, accelerators, peripherals and external IP into the SoC.

Connect subsystems throughinterconnects and NoCs, using AXI, APB and, where applicable, CHI.

Integrate chip IOs and pad connections.

Create and maintainSDC timing constraintswith physical design teams.

Run, debug and closelint, CDC and RDC checks.

Integrate clocks, resets and power infrastructure, contributing to UPF power intent.

Develop Python and C scripts and tests for automation and initial hardware testing.

Resolve integration issues across engineering teams and support delivery through tapeout.

Mandatory Requirements

8+ years in digital or SoC design.





Strong practicalVerilog/SystemVerilog RTL designexperience.

Proven integration of multiple subsystems withinlarge SoCs.

Experience withinterconnects or NoCs, including AXI and APB.

Participation inat least one completed tapeout.

Practical experience withlint, CDC and RDC checks.

Experience managingSDC constraints and chip IO integration.

Working knowledge of Python and C for scripting and automation.

Relevant engineering degree.

Fluent English.

Important:Candidates must demonstrate direct SoC RTL integration experience through tapeout.

Verification experience alone does not meet this requirement.

Optional / Desired

Knowledge of clock, reset and power architectures.

Experience with the CHI coherent interconnect protocol.

Familiarity with UPF power intent and low power design flows.

Pad ring integration experience.

What's in it for you?

Versátil working hours

Hybrid model, 4 days office, 1 day from home

1 week per year working from anywhere

25 days annual leave plus December 24 and 31

Monthly food allowance

Private medical insurance

Relocation bonus

Housing search support

Visa support, subject to approval

Family relocation support, subject to eligibility

Virtual shares, subject to plan terms

Language classes

Tax incentive

📌 Senior Soc Rtl Integration Engineer (Barcelona)
🏢 Hireroo
📍 Barcelona