Analog Devices, Inc. in Madrid, Spain is seeking a Principal Physical Design Engineer to own end-to-end RTL-to-GDSII implementation and signoff for complex SoCs.
You will drive timing closure, select Cadence/Synopsys PD flows, and lead a distributed PD team across locations to meet project milestones. The role requires 10+ years of PD experience and a strong background in floorplanning, CTS, routing, DRC/LVS, and power analysis.
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📌 Senior SoC Physical Design Lead (España)
🏢 Analog Devices
📍 España
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