FPGA Engineer (Rivas-Vaciamadrid)

FPGA Engineer (Rivas-Vaciamadrid)

03 nov
|
Grupo Oesia
|
Rivas-Vaciamadrid

03 nov

Grupo Oesia

Rivas-Vaciamadrid

At Oesia Group, we are growing! We would like to count on you for our next job offer: We are looking for a FPGA Engineer to join an important Project located in Rivas Vaciamadrid in hybrid job modality.

What are we looking for?

- An/a FPGA Engineer, with at least 4 years of experience.
- Availability to join a stable project in Rivas Vaciamadrid .
- Work Model: hybrid

Requirements:

- Advanced synthesizable VHDL
- Verification of logic circuits using VHDL testbenches and a simulator (Modelsim)
- Zynq and Ultrascale+ FPGAs
- Vivado design environment
- Design of user IP cores
- Advanced knowledge of AXI (AXI4-Lite, AXI-MM, AXI-Stream)
- Chipscope proficiency
- TCL scripts on XSCT

What will your responsibilities be?

- Analysis of the mathematical foundations of cryptographic algorithms and optimization techniques
- RTL description of cryptographic algorithms using VHDL and implementation using Xilinx technology
- Functional verification using a sim]]>

📌 FPGA Engineer (Rivas-Vaciamadrid)
🏢 Grupo Oesia
📍 Rivas-Vaciamadrid

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