Our projects become technology that protects, connects and drives strategic sectors: our own. At Grupo Oesía , we work to ensure that innovation has a real impact , and we are looking for people who want to be part of this challenge.

WHAT WILL YOUR MISSION BE?

You will be part of a multidisciplinary team where you will design, develop and integrate technological solutions that become part of high-value projects for our clients.

WHAT WILL YOU DO ON A DAY-TO-DAY BASIS?

- Define and evolve complex SoC and ASIC architectures for advanced integrated circuit developments.
- Design architectures based on RISC‑V, ARM or equivalent processor technologies.
- Define the architecture and integration strategy for third‑party IPs and complex subsystems.
- Make key architectural decisions considering system requirements, integration and implementation constraints throughout the ASIC lifecycle.
- Work closely with Front‑End and Back‑End teams, supporting the evolution of the architecture through implementation.
- Collaborate with verification teams using advanced methodologies such as UVM.
- Support architecture‑related activities throughout DFT, ATPG, MBIST/LBIST, tape‑out and silicon validation.
- Participate throughout the complete ASIC lifecycle, from architecture and design through tape‑out, fabrication and silicon validation.
- Coordinate technical activities with foundries, design houses, technology centres and IP providers.
- Provide technical guidance and contribute to architectural decisions within multidisciplinary ASIC design and engineering teams.

WHAT ARE WE LOOKING FOR?

- Degree in Telecommunications Engineering, Electronics, Industrial Engineering, Computer Engineering or another relevant engineering discipline.
- Professional experience in the architecture and development of complex ASICs and SoCs.
- Participation in at least one complete ASIC development lifecycle.




- Real hands‑on experience in ASIC tape‑outs and integrated circuit fabrication.
- Experience defining complex SoC architectures based on RISC‑V, ARM or equivalent architectures.
- Experience with the integration of third‑party IPs and complex subsystems.
- Knowledge and practical experience in Front‑End and/or Back‑End ASIC flows.
- Experience in advanced verification environments using UVM methodologies.
- Knowledge of DFT, ATPG, MBIST/LBIST and silicon validation.
- Experience using industry‑standard EDA tools such as Cadence, Synopsys or Siemens EDA.
- Experience working with multidisciplinary teams covering design, verification, physical implementation and test.

WHAT WOULD MAKE YOU STAND OUT?

- Direct participation in successful ASIC tape‑outs.
- Experience working across multiple semiconductor technology nodes.
- Experience with semiconductor technologies between 22 nm and 65 nm.
- Strong experience in the definition and evolution of complex SoC architectures.
- Previous experience providing technical leadership to ASIC design teams.
- Experience coordinating technical activities with foundries, design houses, technology centres and IP providers.

WHAT WILL YOU FIND AT GRUPO OESÍA?

- Projects with a real technological impact.
- Teams where sharing knowledge is part of the job.
- Continuous professional development tailored to each role and individual.
- An environment where engineering and people move forward together.

If you are motivated by taking on new technological challenges and being part of projects that leave a lasting mark, we would be delighted to meet you.

About Grupo Oesía

Build your career where technology has a purpose . At Grupo Oesía, we develop dual-use digital and industrial engineering projects in strategic sectors, strengthening key capabilities for Spain and Europe from our technology centres and alongside a team of more than 3,800 professionals based in Spain, Brussels, Latin America and Asia.

Cipherbit -

📌 SoC / ASIC Architect | Semiconductor & Security Technologies (Rivas-Vaciamadrid)
🏢 Cipherbit-Grupo Oesía
📍 Rivas-Vaciamadrid