Our partner is looking for a Senior DDR Design Engineer to design, develop and integrate high performance memory subsystem solutions for advanced semiconductor products. You will work closely with architecture, RTL, verification and implementation teams on memory controller design, interface integration, timing and validation. Barcelona, Spain, Hybrid Level: Senior Design and integrate DDR or HBM memory subsystems Implement and review RTL using Verilog or VHDL Apply timing constraints and support timing analysis and closure Perform block level testing and validation Contribute to design reviews and technical decisions Proven memory controller design or integration experience ~ RTL design using Verilog or VHDL ~ Block level testing and validation ~ Master or PhD Python, Perl, Bash or Tcl Broader knowledge of memory architecture and system performance What’s in it for you? ~ Adaptable

working hours
~ Hybrid model, 4 days office, 1 day from home ~Private medical insurance ~ Relocation bonus ~ Visa support if required ~ Family relocation support ~ Virtual shares ~ Tax incentive, subject to eligibility #

📌 Design Engineer (Barcelona)
🏢 Hireroo
📍 Barcelona