03 nov
|
Universidad Politécnica de Madrid
|
España
03 nov
Universidad Politécnica de Madrid
España
UNIVERSIDAD POLITECNICA DE MADRID invites applications for a First Stage Researcher (R1) in the Engineering field. The project focuses on fault-tolerant and real-time concepts for RISC-V, including safety islands and physical design for safety-critical cores.
The adecuado candidate holds a Master’s degree in Electrical/Electronics Engineering or Computer Science and demonstrates proficiency in Verilog/VHDL, RISC-V, and C/C++.
📌 RISC-V Safety (España)
🏢 Universidad Politécnica de Madrid
📍 España