About the Role
We are looking for experienced Design Verification Engineers to join our semiconductor engineering team and work on challenging IP and SoC verification projects. We are particularly interested in engineers with strong experience in Ethernet IP verification, including MAC, PCS and PHY components. Experience with high-speed communication protocols and complex SoC verification is highly valued.

Key Responsibilities
• Perform IP, subsystem and system-level verification of complex semiconductor designs.
• Develop and execute verification plans, test scenarios and testbenches.
• Verify Ethernet IP, particularly MAC, PCS and PHY blocks.
• Develop and maintain SystemVerilog/UVM-based verification environments.
• Implement tests, analyze functional coverage and drive coverage closure.
• Debug simulation failures and collaborate with design teams to resolve issues.
• Support verification of high-speed interfaces and complex SoC architectures.




• Contribute to regression environments and verification automation. Required Skills & Experience
• Solid experience in ASIC/SoC Design Verification.
• Strong knowledge of SystemVerilog and UVM.
• Hands-on experience with Ethernet IP verification (MAC, PCS and/or PHY) is a major advantage.
• Experience with block-level and system-level verification.
• Experience with PCIe verification.
• Experience with RISC-V or complex SoC architectures.
• Programming skills in C/C++ and/or Python.
• Experience with Linux and simulation tools.
• Familiarity with Cadence verification tools. Interested? If you have experience in Design Verification, particularly with Ethernet IP, we would be happy to hear from you. Send us your CV or get in touch to discuss the opportunity.

📌 Senior Design Verification Engineer (España)
🏢 TechTeamz
📍 España