Beagle is seeking an experienced Lead Design Verification Engineer to own the verification of high‑speed interfaces in cutting‑edge AI So C designs. You will architect System Verilog/UVM environments, drive coverage plans, and lead a team toward sign-off. Required are 10+ years in ASIC/So C verification, deep PCIe/UCIe and AMBA protocol knowledge, and hands‑on ability with System Verilog/UVM. Strong leadership and collaboration across RTL, firmware and architecture are essential.
📌 Verification Architect For Ai Soc (Madrid)
🏢 Beagle
📍 Madrid