Beagle is seeking an experienced Lead Design Verification Engineer to own the verification of high?speed interfaces in cutting?edge AI SoC designs.
You will architect SystemVerilog/UVM environments, drive coverage plans, and lead a team toward sign-off.
Required are 10+ years in ASIC/SoC verification, deep PCIe/UCIe and AMBA protocol knowledge, and hands?on ability with SystemVerilog/UVM.
Strong leadership and collaboration across RTL, firmware and architecture are essential.
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📌 Verification Architect For Ai Soc (España)
🏢 Beagle
📍 España
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