We are currently looking for an experienced Lead Design Verification Engineer to join an innovative semiconductor business developing advanced AI SoC and high-performance silicon technologies. This is an exciting opportunity for a senior verification specialist to take technical ownership of complex subsystem and IP-level verification, focusing on high-speed interface protocols and next-generation SoC architectures.

Key Responsibilities
* Lead subsystem and IP-level functional verification of high-speed interfaces within complex AI SoC designs.
* Architect, develop and maintain reusable SystemVerilog/UVM-based verification environments, testbenches and components.
* Provide technical expertise across high-speed protocols, including PCIe, UCIe and SerDes, alongside AMBA protocols such as AXI, AHB, CHI and CXS.
* Define verification strategies, test plans, coverage models and sign-off criteria.
* Lead, mentor and support verification engineers, driving quality and delivery through to sign-off.
* Debug complex RTL and functional issues, perform root-cause analysis and collaborate with design and architecture teams.
* Optimise simulation, regression, automation and coverage-analysis flows.




* Work closely with RTL design, SoC architecture, firmware and cross-functional engineering teams to resolve integration challenges. Experience Required
* Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or a related discipline.
* 10+ years of ASIC/SoC design verification experience, including recent hands-on high-speed interface verification.
* Strong expertise in PCIe, UCIe, SerDes or related high-speed communication protocols.
* In-depth knowledge of AMBA protocols, including AXI, AHB, CHI and CXS.
* Extensive experience with SystemVerilog, UVM, testbench development and coverage-driven verification.
* Proven track record of functional coverage closure and verification sign-off.
* Strong understanding of digital design principles, SoC architectures and subsystem integration.
* Experience with industry-standard simulation tools such as Synopsys VCS, Cadence Xcelium or Siemens Questa.
* Demonstrable technical leadership, mentoring and cross-functional collaboration skills. #J-18808-Ljbffr

📌 Lead Design Verification Engineer (España)
🏢 Beagle
📍 España