Ciklum in Spain is seeking a Senior Logic Design Engineer to join our cross-functional team and help build next-generation FPGA/ASIC platforms for demanding realtime applications. You will design and optimize low-latency System Verilog RTL, work with system architects, verification, software and hardware specialists in an international environment, and drive the RTL development lifecycle from architecture to verification. #J-18808-Ljbffr
📌 Senior fpga/asic logic design engineer (Madrid)
🏢 Ciklum
📍 Madrid