27 oct
|
Beagle
|
Barcelona
Beagle is seeking an experienced Lead Design Verification Engineer to lead subsystem and IP‑level verification of AI SoC designs. You will own verification strategies and sign‑off, architect reusable SystemVerilog/UVM environments, and mentor engineers across RTL, architecture, and firmware teams.
The role requires 10+ years in ASIC/SoC verification, strong PCIe/UCIe/SerDes and AMBA protocol expertise, and hands-on experience with industry tools like VCS, Xcelium, and Questa.
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📌 Lead AI SoC Verification Architect (Barcelona)
🏢 Beagle
📍 Barcelona