Write new eval tasks where a model designs one passive on-chip component to a spec (e.g., a spiral inductor with a target inductance, quality factor and area), then simulates it and iterates.
For each task, write the spec, a reference design that meets it and an automatic check that re-simulates the submitted layout and compares the results with the spec.
Start with a pilot of 5 tasks, then iterate with us before scaling.
What They'd DoWrite new eval tasks where a model designs one passive on-chip component to a spec (e.g., a spiral inductor with a target inductance, quality factor and area), then simulates it and iterates.
For each task, write the spec, a reference design that meets it and an automatic check that re-simulates the submitted layout and compares the results with the spec.
Start with a pilot of 5 tasks, then iterate with us before scaling.
Must haveHands-on RF IC design, including laying out passives (e.g., spiral inductors, transformers and baluns,



transmission lines, coupled resonators, quadrature hybrids).
Has run EM simulations on their own layouts and can read the results (e.g., S-parameters, inductance and quality factor).
Works with GDS layouts and S-parameter files.
Enough Python to script simulations and write the checks.
Nice to haveExperience with IHP SG13G2 or another open PDK (our test chip is a 24 GHz radar receiver front end on SG13G2).
The open-source tools we use: KLayout, Palace, openEMS, ngspice, scikit-rf. We can share our container (IIC-OSIC-TOOLS).
Commercial EM solvers (e.g., Cadence EMX or Ansys HFSS).
SPICE simulation of RF blocks (e.g., a low noise amplifier), which we'd like to cover later.

Location:
Europe, Canada, USFinal rate depends on qualifications, expertise, experience, and location

📌 Analogue RF IC Designer for EM Simulation Tasks (España)
🏢 Braintrust
📍 España