Aion Silicon Ltd seeks a seasoned Principal Engineer for So C Physical Design to lead complex ASIC/So C implementations from architecture to tape-out. You will drive full-chip physical design, floorplanning, power/clock planning, PMU strategies, and signoff, collaborating across Architecture, RTL, Verification, DFT, STA, Packaging, and Silicon Validation teams. Adecuado candidates bring 15+ years of ASIC/So C PD experience, a proven tape-out record, and deep expertise in 22nm and below nodes, #J-18808-Ljbffr
📌 Senior soc physical design architect: tape-out lead (Madrid)
🏢 Aion Silicon
📍 Madrid
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