26 oct
|
Beagle
|
Barcelona
Beagle is seeking an experienced Lead Design Verification Engineer to lead subsystem and IP‑level verification of AI So C designs. You will own verification strategies and sign‑off, architect reusable System Verilog/UVM environments, and mentor engineers across RTL, architecture, and firmware teams. The role requires 10+ years in ASIC/So C verification, strong PCIe/UCIe/Ser Des and AMBA protocol expertise, and hands-on experience with industry tools like VCS, Xcelium, and Questa. #J-18808-Ljbffr
📌 Lead Ai Soc Verification Architect (Barcelona)
🏢 Beagle
📍 Barcelona