The Senior Physical Design Engineer supports the end-to-end physical implementation and signoff of digital blocks and SoCs. Working as part of a collaborative and potentially geographically distributed engineering team, the role applies practical physical design knowledge to deliver high-quality implementation results while developing technical depth across the RTL-to-GDSII flow.
Key Responsibilities
- Execute assigned RTL-to-GDSII implementation activities, including floor-planning, CTS, routing, equivalence checking, timing closure, and physical verification.
- Use Cadence or Synopsys based physical design flows to support implementation, optimisation, and signoff activities.
- Apply a good working knowledge of synthesis and timing constraints to review implementation results and provide informed feedback to the design team.
- Analyse and resolve timing, power, IR/EM, DRC, and LVS issues with guidance from senior engineers where required.
- Strong communication, and teamwork skills, with a willingness to learn and take ownership of assigned implementation tasks.
Qualifications
- B.Tech., M.Tech., or equivalent qualification in Electrical Engineering, Electronics Engineering, or a related discipline.
- Approximately 3–7 years of relevant physical design or digital implementation experience.
- Hands-on experience with industry-standard physical design and signoff tools, preferably within a Cadence or Synopsys environment.
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Job Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/Days