As a Functional Verification Engineer, you will be interfacing with architecture, design, physical implementation and software teams in order to make sure that the systems are performing to the highest level. Developing Verification environment development and maintenance in SystemVerilog/UVM/SystemC/C++, including all the respective components such as Stimulus, Checkers, Assertions, Trackers, and Coverage.
Executing Verification Plans, including Design Bring-up, DV environment Bring-up, Regressions and Debug of the test failures.
Using the standard tools and flows of the verification process (Simulators, Coverage Analyzers, Unix, Continuous Integration, Bug Tracking, ...). Create and execute testcases to verify the functionality, performance, and robustness in embedded C and SV.
Work closely with cross-functional teams to achieve verification closure,



conducting coverage analysis, bug tracking, and regression testing to ensure the quality and completeness of verification activities.
Min 5 years of experience in relevant field of Verification of complex SoC or IPExperience inSystemVerilog/UVMSystemC/C++Experience in Constrained random, Functional Coverage development, design debug.
Some knowledge of scripting languages like Bash/Perl/Python.
Good level of English, both written and spoken is mandatory.
Soft KillsTeam player, able to work with multiple cultures both on site and remotely.
Enjoy a hybrid work environment.
At Openchip & Software Technologies S.
L.,

📌 Validatie Ingenieur in engineering (España)
🏢 Openchip & Software Technologies
📍 España