Ciklum in Spain is seeking a Senior Logic Design Engineer to join our cross-functional team and help build next-generation FPGA/ASIC platforms for demanding realtime applications. You will design and optimize low-latency SystemVerilog RTL, work with system architects, verification, software and hardware specialists in an international environment, and drive the RTL development lifecycle from architecture to verification. #J-18808-Ljbffr
📌 Senior FPGA/ASIC Logic Design Engineer (Santiago de Compostela)
🏢 Ciklum
📍 Santiago de Compostela
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