We are looking for a Design Verification Engineer to support gate-level simulation (GLS) and hardware emulation activities for our AI chip design and verification teams. This is a hands-on role requiring close collaboration with RTL design, DFT, physical design, and firmware teams.
Set up, run, and debug gate-level simulations (GLS) for functional, timing (SDF back-annotated), and low-power verification across multiple design blocks and full-chip levels.
Support hardware emulation platforms Siemens Veloce including design compilation, bring-up, debug, and regression management.
Work with physical design and STA teams to resolve SDF annotation, timing exceptions, and back-annotated simulation discrepancies.
Bring up emulation models for pre-silicon software/firmware validation and performance profiling.
Bachelor's or Master's degree in Electrical Engineering,



Computer Engineering, or related field.
~3+ years of experience in ASIC/SoC design verification, with direct exposure to gate-level simulation.
~ Strong understanding of digital design fundamentals: clocking, reset strategies, low-power design (UPF/CPF), and STA concepts
~ Scripting skills in Perl, Python, or TCL for flow automation and debug.
~ Familiarity with version control (Git/Perforce) and job scheduling systems (LSF/Grid).
~ Experience bringing up firmware or software on emulation platforms.
Knowledge of physical design flows and their interaction with timing closure
4 days per week in the Barcelona office (city center), 1 day WFH.
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📌 Senior Design Verification Engineer (Barcelona)
🏢 Semidynamics
📍 Barcelona