Senior Verification Engineer – Drive Quality in Next‐Gen RISC‐V CPUs (UVM/SystemVerilog) Overview At Akuaro, we are proudly leading the recruitment process for our partner — a European deep-tech company redefining what's possible in high-performance computing and digital infrastructure. Specialized in cutting-edge RISC-V systems and backed by major innovation initiatives, our partner is assembling a world-class engineering team in Barcelona. They are now seeking a Senior Verification Engineer with expertise in SystemVerilog and UVM to ensure their next generation of high-performance silicon meets the highest quality standards. Contract: Permanent – Internal team of our partner Why This Role Is Unique
* Join the forefront of Europe's semiconductor revolution in CPU design and verification.
* Verify cutting-edge RISC-V processors destined for high-performance computing applications.
* Use the latest advanced verification methodologies (UVM, formal verification) on complex, modern microarchitectures.
* Full-cycle ownership – contribute from block-level verification to full system validation.
* Influence design quality from day one; your work directly impacts first-silicon success. What You'll Be Doing
* Develop and maintain UVM-based testbenches for complex digital designs (CPU cores, SoC blocks).
* Define and implement comprehensive verification plans, covering all features and corner cases.
* Write and run directed and constraint-random tests to validate functionality and performance.
* Implement checkers and monitors in SystemVerilog to verify correctness of microarchitectural features.
* Execute extensive simulations and regression suites; analyze waveform dumps to debug failing tests.
* Use coverage-driven verification (functional and code coverage) to measure progress and target gaps.
* Apply formal verification techniques to prove critical properties and catch corner-case bugs.
* Automate workflows with scripting (Python/Perl/Bash/TCL)



for regression management and result analysis.
* Collaborate closely with design and RTL teams to review specifications, discuss bugs, and drive fixes to closure. What You Bring
* Master's or PhD in Electronic Engineering, Computer Engineering, or related field.
* 8+ years of experience in digital design verification.
* Proven expertise in SystemVerilog and UVM for complex ASIC/SoC verification.
* Strong scripting skills (Python, Perl, Bash, or Tcl) to automate verification flows and data analysis.
* Hands-on experience with simulation tools (e.g., ModelSim, VCS, Xcelium) and waveform debugging.
* Familiarity with coverage metrics and coverage closure strategies.
* Knowledge of formal verification tools/methods (property checking, equivalence checking) is a plus.
* Experience verifying both block-level modules and full system-level integrations.
* Proficiency with version control systems (Git, SVN) in collaborative engineering projects.
* Excellent problem-solving abilities and attention to detail – able to root-cause intricate bugs.
* Strong communication and teamwork skills, collaborating effectively with cross-functional teams.
* English fluency (C1 or higher). What's in It for You
* Versátil

working hours
– Focus on outcomes, not just schedules.
* Competitive compensation – Recognizing your expertise and impact.
* Learning-driven culture – Work with top-tier engineers on cutting-edge projects; continuous growth encouraged.
* Visa sponsorship – Open to international talent; relocate to a vibrant tech hub.
* Candies, coffee, and free Spanish lessons – Enjoy a welcoming office culture while settling into life in Barcelona.
* Barcelona HQ – Where tech innovation meets Mediterranean lifestyle.
* Ready to Build the Future of Chips in Europe? If you're passionate about verification and want to play a key role in one of Europe's most exciting deep-tech projects, we want to hear from you. Apply now — Akuaro is exclusively managing this hiring process for our partner. Let's connect and explore this opportunity together.

📌 Senior Verification Engineer (Barcelona)
🏢 Akuaro
📍 Barcelona