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Analog Devices "Platform IP" organization is seeking an experienced Senior Layout & Design Automation Engineer to join our growing team. This role combines deep expertise in analog and mixed-signal IC layout with a passion for engineering productivity, automation, and IP reuse.

The successful candidate will be responsible for delivering complex block and subsystem layouts while also driving continuous improvement of layout methodologies, automation frameworks, and reusable IP infrastructure. The engineer will collaborate closely with circuit designers, layout engineers, EE teams, and technology experts to enable high-quality silicon solutions across multiple business units and process technologies.

This position is ideally suited to an engineer who is equally comfortable solving challenging physical design problems and developing automation solutions that improve engineering efficiency at scale.

Key Responsibilities

Technical Layout Leadership

Lead development of complex analog and mixed-signal layouts from floorplanning through tapeout. Own layout execution for critical IP, subsystems, and test-chip developments. Drive high-quality layout implementation for:Data converters (ADCs/DACs)Power management circuits (LDOs, references, regulators)Amplifiers and signal chain circuitsPLLs and clock-generation circuitsHigh-voltage and mixed-voltage designs Ensure designs meet performance, matching, reliability, ESD, latch-up, and manufacturability requirements. Drive successful DRC, LVS, ERC, EMIR and parasitic extraction closure.





Design Automation & Productivity

Develop and deploy automation solutions that improve layout productivity and design quality. Identify repetitive engineering tasks and implement scalable solutions. Support advanced methodologies including:Automated layout generationLayout verification automationIP qualification workflowsReusable analog building blocksAI-assisted design and productivity initiatives Partner with CAD and EDA teams to improve design flows and tool integration.

IP Development & Reuse

Contribute to the development of reusable Platform IP across multiple technology nodes. Support IP migration, qualification, and reuse activities. Promote best practices for containerized IP, version control, and design traceability. Assist in defining scalable methodologies that enable reuse across business units and geographical teams.

Technical Leadership & Mentorship

Provide technical guidance to layout engineers across the organization. Perform layout reviews and design audits. Mentor junior and mid-level layout engineers. Contribute to engineering standards, training material, and best-practice documentation.



Act as a recognized subject matter expert in one or more technical domains.

Required Qualifications

BS, MS, or equivalent experience in Electrical Engineering, Electronics Engineering, or related discipline. 8+ years of analog or mixed-signal IC layout experience. Proven experience delivering silicon in advanced and mature process technologies. Expert knowledge of:Cadence VirtuosoLayout XL / VXL methodologiesCalibre DRC, LVS, ERC and extraction flows Deep understanding of:Device matchingParasitic effectsShielding and isolation techniquesReliability and ESD considerationsPower distribution and substrate management Scripting and automation experience using one or more of:SKILLPythonShell/BashTcl

Preferred Qualifications

Experience developing engineering automation deployed to multiple users. Experience with analog layout generators and parameterized cell development. Familiarity with AI-assisted engineering workflows. Experience supporting IP libraries shared across multiple design groups. Knowledge of multiple foundries and process nodes. Experience working with distributed integral engineering teams. Previous technical leadership or project-lead responsibility.

Success Profile

A successful candidate will:

Consistently deliver high-quality layouts on complex projects. Improve engineering productivity through automation and workflow enhancement. Influence layout methodology across projects and teams. Champion IP reuse and standardization. Mentor engineers and raise the technical

📌 Staff Layout (Valencia)
🏢 Analog Devices
📍 Valencia