As a Senior Layout & Design Automation Engineer, you will lead complex analog/mixed-signal layouts from floorplanning to tapeout and drive reusable IP infrastructure. You will partner with circuit designers and EDA teams to ensure high-quality silicon across process technologies. You will champion automation to boost productivity and design quality at scale. This role offers the opportunity to influence layout methodology and contribute to Platform IP across multiple business units.
Responsabilidades
- Lead development of complex analog and mixed-signal layouts from floorplanning through tapeout
- Own layout execution for critical IP, subsystems, and test-chip developments
- Ensure layouts meet performance, matching, reliability, ESD, latch-up, and manufacturability requirements
- Drive DRC, LVS, ERC, EMIR and parasitic extraction closure
- Develop and deploy automation solutions to improve layout productivity and quality
- Identify repetitive tasks and implement scalable automation
- Partner with CAD/EDA teams to improve flows and tool integration
- Contribute to IP development, migration, qualification, and reuse activities
- Provide technical guidance, perform design reviews, and mentor engineers
Requisitos principales
- 8+ years of analog or mixed-signal IC layout experience
- Proven experience delivering silicon in advanced and mature process technologies
- Expert knowledge of Cadence Virtuoso, Layout XL/VXL, Calibre DRC/LVS/ERC and extraction flows
- Deep understanding of device matching, parasitics, shielding, reliability and ESD, power distribution
- Scripting/automation experience with SKILL, Python, Shell/Bash, Tcl