Specialization: Equivalence Checking and Low Power VerificationJob Description
Our partner is looking for an experienced Formal Verification Lead to ensure functional equivalence and correct power behavior across complex semiconductor designs.
The role focuses on Logic Equivalence Checking (LEC), UPF verification, debugging and signoff, working closely with RTL, synthesis and physical design teams.
Location: Barcelona, Spain
Working model: Hybrid
Employment: Full time
Responsibilities
- Perform RTL to Gate and Gate to Gate equivalence checking.
- Verify power intent using UPF and investigate functional mismatches.