Senior engineer for end-to-end physical implementation and signoff of digital blocks and So Cs, collaborating with a distributed team to deliver RTL-to-GDSII results and drive design closure. Requires experience with Cadence or Synopsys flows and a strong background in timing, DRC/LVS, and floorplanning.
📌 Principal Physical Design Engineer (Valencia)
🏢 Analog Devices
📍 Valencia
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