Aion Silicon Ltd in Barcelona is seeking a Principal STA/Constraints Sign-Off Engineer to lead timing signoff and constraint methodology development for advanced-node SoC and IP designs. You will drive signoff closure across SDCs, MMMC, and ECOs while enabling tape-outs with optimal performance, power, and area. You will collaborate with Architecture, RTL, Verification, DFT and PD teams, mentoring engineers and developing automation to streamline flows.
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📌 Principal STA & Constraints Signoff Architect (Madrid)
🏢 Aion Silicon
📍 Madrid
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