16 oct
|
Arquimea
|
Casares
ARQUIMEA seeks an FPGA Design Engineer to craft and verify digital hardware for FPGAs, ASICs and SoCs for space and defense programs. You will define architectures, implement RTL, and lead verification from requirements to sign-off in a multinational team based in Madrid.
The candidate should have 5+ years in FPGA/digital hardware, HDL/VHDL/Verilog experience, and proficiency with Vivado and verification tools. English required; Spanish is a plus. Travel to EU/US may be required.
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📌 FPGA Design Engineer for Space & Defense (Casares)
🏢 Arquimea
📍 Casares