Job DescriptionOur partner is looking for aDesign Verification Engineerto support gate level simulation and hardware emulation for advanced semiconductor designs.The role focuses on validating synthesized designs, identifying timing and functional issues, and supporting hardware emulation before silicon production. You will collaborate with RTL, DFT, physical design and firmware teams.Location:Barcelona, Spain, HybridLevel:Mid / Senior, depending on experienceResponsibilitiesConfigure and debug gate level simulations (GLS)Perform functional, timing and power verificationSupport hardware emulation and system bring-upDebug RTL and netlist mismatchesInvestigate timing, reset and X propagation issuesImplement SDF timing annotationAutomate simulation and emulation workflowsSupport scan, ATPG and BIST verificationEnable firmware testing through emulationImprove simulation performance and regression efficiencyCollaborate with RTL,



DFT and physical design teamsRequirements3+ years of ASIC or SoC verification experienceDegree in Electrical or Computer Engineering or related fieldPractical gate level simulation experienceHardware emulation or FPGA prototyping experienceVerilog/SystemVerilogVCS, Xcelium or QuestaSDF annotation and timing simulationClocking, reset and STA fundamentalsLow power concepts, UPF/CPFPython, Perl or TCL scriptingGit/Perforce and LSF/GridStrong debugging and problem solving skillsOptional / DesiredSiemens Veloce, Cadence Palladium or Synopsys ZeBuUVM verificationDFT, scan, ATPG and MBISTUPF simulation and power verificationFirmware bring-up on emulationLarge SoC verificationPhysical design and timing closure knowledgeEmulation performance optimizationWhat's in it for you?Versátil working hoursHybrid model, 4 days office, 1 day from home1 week per year working from anywhere25 days annual leave plus December 24 and 31Monthly food allowancePrivate medical insuranceRelocation bonusHousing search supportVisa support, subject to approvalFamily relocation support, subject to eligibilityVirtual shares, subject to plan termsLanguage classesTax incentive, subject to eligibility#J-18808-Ljbffr

📌 Design Verification Engineer, Gls & Hardware Emulation (Madrid)
🏢 Hireroo
📍 Madrid