We are seeking a highly motivated and experienced Principal Engineer - So C Physical Design or Chip-Level Expert to lead the implementation of complex ASIC/So C designs from architecture definition through successful tape-out. The idóneo candidate will have deep expertise in full-chip physical design, So C integration, advanced-node implementation, and cross-functional technical leadership. This role requires a strong hands-on technical leader who can drive methodology, execution, and signoff while collaborating closely with Architecture, RTL, Verification, DFT, STA, Package, and Silicon Validation teams. Key Responsibilities Partner with Front-End and Architecture teams to understand chip architecture and drive physical design considerations early in the development cycle. Lead full-chip physical implementation activities including floorplanning, power planning, clock implementation, place-and-route, timing closure, and signoff. Drive physical design methodologies, best-known methods (BKMs), checklists, and implementation guidelines across projects. Serve as the technical focal point for physical design execution and coordinate activities across block, subsystem, and top-level implementation teams. Define project milestones, track progress, manage dependencies, and drive execution to meet tape-out schedules. Collaborate with STA, DFT, RTL, Verification, Power Integrity, and Packaging teams to achieve project goals. Drive closure of timing, congestion, power, IR drop, EM, signal integrity, and physical verification requirements. Debug and resolve design, flow, and methodology issues, identifying scalable solutions and driving implementation. Mentor engineers and contribute to the continuous improvement of design methodologies and automation flows.



Required / Preferred Qualifications B. Tech / M. Tech in Electrical Engineering, Electronics, Computer Engineering, or related discipline. 15+ years of ASIC/So C Physical Design experience. Proven track record of multiple successful So C/ASIC tape-outs. Strong understanding of ASIC/So C integration, including floorplanning, clock distribution, power distribution networks, global signal planning, I/O planning, and hard IP integration. Experience addressing complex So C challenges involving multiple voltage domains, multiple clock domains, ESD implementation strategies, mixed-signal integration, and package-aware design considerations. Solid knowledge of hierarchical and top-down design methodologies, budgeting techniques, timing convergence, and physical convergence strategies for large-scale So Cs. Experience integrating IPs from both internal and external vendors and driving physical implementation requirements throughout the design lifecycle. Hands-on experience with large-scale So Cs exceeding > 20 M gates and operatingat frequencies greater than 1 GHz. Strong understanding of physical design databases, data management, and implementation-signoff consistency. Experience in advanced technology nodes including 22nm, 16nm, 7nm, 5nm, and below. Strong leadership skills with the ability to drive execution across geographically distributed teams. Experience leading or contributing to multiple successful full-chip So C tape-outs with ownership of implementation, timing closure, power integrity, physical verification, and signoff. Tools Required Physical Verification: Calibre, IC Validator (ICV), Pegasus. Power Integrity & Signoff: Red Hawk, Voltus, Prime Power. Scripting & Automation: TCL, Perl, Python, Shell scripting. #J-18808-Ljbffr

📌 Principal Engineer – Soc Physical Design Or Chip-Level Expert (Barcelona)
🏢 Aion Silicon
📍 Barcelona