You will own the power distribution network from voltage regulator output to die bump - impedance, IR drop, droop and decoupling across package and board.

Senior IC role: you own the PDN numbers that power delivery, SI and the package team design against.

What you will work on:

PDN design and closure for a multi-die AI accelerator package

DC IR, AC impedance, transient droop and electro-thermal analysis across die, package and board

Decoupling strategy and optimisation across on-die, package and board tiers

Package-board anti-resonance identification and mitigation

PDN noise to jitter translation, closed back into the SI budget

Responsibilities

Analysis & closure: Build and close DC IR, electro-thermal, AC impedance and transient PDN analysis from VR output through package to die bump. Set target impedance per rail and hold the design to it.

Chip power models: Work with CPM and workload current profiles to size on-die, package and board decoupling, and to predict droop across all three droop timescales.

Resonance & mitigation: Identify package-board anti-resonance and cavity behaviour, and drive the plane, via and decap changes that mitigate it.

SI coupling: Translate PDN noise into jitter through PHY supply sensitivity, and feed the result back into the channel budget.

Vendor & validation: Drive CPM and model requirements with IP, PHY and package vendors. Correlate against PDN impedance measurement and on-die droop telemetry,



and support bring-up and power debug.

Requirements

8+ years in power integrity for high-speed digital systems, including package-level PDN work

Hands-on with PDN extraction and simulation tools - Ansys SIwave/HFSS, Cadence Sigrity/Clarity or equivalent

Real experience with DC IR, target impedance, transient droop and decap optimisation on a high-current rail

Working knowledge of chip power models and how to apply workload current profiles

Comfortable reading a package substrate stackup and bump map, and reasoning about plane, via and cavity behaviour

Python scripting for automation and post-processing

Nice to Have

2.5D, interposer, chiplet or advanced substrate PDN co-design

PDN impedance measurement and on-die margin or droop telemetry correlation

Electro-thermal co-simulation with the thermal team

Familiarity with OCP rack-scale platforms and high-current delivery architectures

Automated or AI-assisted engineering flows - PyAEDT, scikit-rf or similar

Why Semidynamics?

Work for one of Europe’s most promising deep-tech semiconductor scale-ups.

Accelerated development path.

4 days per week in the Barcelona office (city center), 1 day WFH.

1 week of work from everywhere in the world.

Competitive package.

A collaborative, technical, and growth-oriented environment that values direct ownership and clear thinking.

📌 Senior Power Integrity Engineer (Madrid)
🏢 Semidynamics
📍 Madrid