We are looking for a Design Verification Engineer to support gate-level simulation (GLS) and hardware emulation activities for our AI chip design and verification teams. In this role, you will help ensure silicon correctness by validating post-synthesis netlists, debugging timing and reset issues, and enabling large-scale emulation of SoC designs prior to tapeout. This is a hands-on role requiring close collaboration with RTL design, DFT, physical design, and firmware teams. Key Responsibilities * Set up, run, and debug gate-level simulations (GLS) for functional, timing (SDF back-annotated), and low-power verification across multiple design blocks and full-chip levels. * Support hardware emulation platforms Siemens Veloce including design compilation, bring-up, debug, and regression management. * Debug mismatches between RTL and gate-level simulation results, including X-propagation, timing violations, glitches, and clock/reset domain issues. * Develop and maintain testbenches, scripts, and flows to automate GLS and emulation compile/run cycles.



* Collaborate with DFT engineers to validate scan, ATPG patterns, and BIST in gate-level and emulation environments. * Work with physical design and STA teams to resolve SDF annotation, timing exceptions, and back-annotated simulation discrepancies. * Bring up emulation models for pre-silicon software/firmware validation and performance profiling. * Triage and root-cause simulation/emulation failures, track bugs, and drive issues to closure with cross-functional teams. * Optimize simulation and emulation runtimes, capacity, and compile turnaround for large SoC designs. * Maintain documentation of GLS/emulation methodologies, flows, and known issues. Requirements * Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. * 3+ years of experience in ASIC/SoC design verification, with direct exposure to gate-level simulation. * Hands-on experience with at least one hardware emulation pla

📌 Design Verification Engineer – GLS (Cataluña)
🏢 Semidynamics
📍 Cataluña