Job Description

Our partner is looking for a

DFT Engineer

to support DFT implementation, test development and production readiness for complex SoC and SiP designs.
You will work across pre silicon and post silicon stages, collaborating with design, validation, packaging, operations, external IP providers and EDA vendors. The role focuses on improving testability, manufacturability, test coverage, yield and production quality across advanced semiconductor programs.
Level:

Mid
Location:

Barcelona, Spain, Hybrid
Responsibilities

Define and implement DFT architectures

Insert and validate scan chains, BIST and JTAG

Support DFT integration across SoC and SiP designs

Develop silicon, package and system level test strategies

Develop automated production and characterization test solutions

Improve test coverage, test time, cost and production efficiency

Support post silicon test optimization, silicon debug and yield analysis

Work with design and validation teams to resolve DFT related issues

Collaborate with packaging, operations, IP providers and EDA vendors





Contribute to DFT methodology and process improvements

Support production readiness and test quality through development and ramp

Requirements

4+ years of DFT, silicon test or related semiconductor experience

Tessent and SSN experience

Experience integrating Tessent or SSN methods with advanced node EDA flows

Experience with SoC or SiP tape outs

Strong understanding of scan chains, BIST and JTAG

DFT architecture and implementation experience

Post silicon test optimization and yield analysis

Experience defining production test strategies

Understanding of silicon characterization and test coverage

SystemVerilog and Verilog

Shell, Tcl or Python scripting

Ability to work across design, validation and manufacturing teams

Bachelor, Master or PhD in Electrical Engineering, Computer Engineering or related field

Preferred / Valued Knowledge

RISC V architecture , especially within SoC, RTL, verific

📌 DFT Engineer (Madrid)
🏢 Hireroo
📍 Madrid